12. ISCA 1985:
Boston,
MA,
USA
Proceedings of the 12th Annual Symposium on Computer Architecture,
June 1985,
Boston,
MA,
USA
- Viktor K. Prasanna, Cauligi S. Raghavendra:
Array Processor with Multiple Broadcasting.
2-10
- G. Wolf, J. Robert Jump:
Matrix Multiplication in an Interleaved Array Processing Architecture.
11-17
- James R. Goodman, Jian-tu Hsieh, Koujuch Liou, Andrew R. Pleszkun, P. B. Schechter, Honesty C. Young:
PIPE: A VLSI Decoupled Architecture.
20-27
- Peter Y.-T. Hsu, Joseph T. Rahmeh, Edward S. Davidson, Jacob A. Abraham:
TIDBITS: Speedup Via Time-Delay Bit-Slicing in ALU Design for VLSI Technology.
28-35
- James E. Smith, Andrew R. Pleszkun:
Implementation of Precise Interrupts in Pipelined Processors.
36-44
- Makoto Hasegawa, Yoshiharu Shigei:
High-Speed Top-of-Stack Scheme for VLSI Processor: a Management Algorithm and Its Analysis.
48-54
- Charles Y. Hitchcock III, Brinkley Sprunt:
Analyzing Multiple Register Sets.
55-63
- Alan Jay Smith:
Cache Evaluation and the Impact of Workload Choice.
64-73
- David A. Moon:
Architecture of the Symbolics 3600.
76-83
- Ashwin Ram, Janak H. Patel:
Parallel Garbage Collection Without Synchronization Overhead.
84-90
- Gurindar S. Sohi, Edward S. Davidson, Janak H. Patel:
An Efficient LISP-Execution Architecture with a New Representation for List Structures.
91-98
- Hideharu Amano, Taisuke Boku, Tomohiro Kudoh, Hideo Aiso:
(SM)²-II: A New Version of the Sparse Matrix Solving Machine.
100-107
- John F. Beetem, Monty Denneau, Don Weingarten:
The GF11 Supercomputer.
108-115
- Bradley Warren Smith, Howard Jay Siegel:
Models for Use in the Design of Macro-Pipelined Parallel Processors.
116-123
- Jan Edler, Allan Gottlieb, Clyde P. Kruskal, Kevin P. McAuliffe, Larry Rudolph, Marc Snir, Patricia J. Teller, James Wilson:
Issues Related to MIMD Shared-memory Computers: The NYU Ultracomputer Approach.
126-135
- Roland N. Ibbett, P. C. Capon, Nigel P. Topham:
MU6V: A Parallel Vector Processing System.
136-144
- Stephen F. Lundstrom:
A Decentralized Control, Highly Concurrent Multiprocessor.
145-151
- William J. Dally, James T. Kajiya:
An Object Oriented Architecture.
154-161
- Edward F. Gehringer, James Leslie Keedy:
Tagged Architecture: How Compelling Are its Advantages?
162-170
- S. Nanba, N. Ohno, H. Kubo, H. Morisue, T. Ohshima, H. Yamagishi:
VM/4: ACOS-4 Virtual Machine Architecture.
171-178
- Tep P. Dobry, Alvin M. Despain, Yale N. Patt:
Performance Studies of a Prolog Machine Architecture.
180-190
- Ryosei Nakazaki, Akihiko Konagaya, Shinichi Habata, Hideo Shimazu, Mamoru Umemura, Masahiro Yamamoto, Minoru Yokota, Takashi Chikayama:
Design of a High-speed Prolog Machine (HPM).
191-197
- Nam Sung Woo:
A Hardware Unification Unit: Design and Analysis.
198-205
- Nicholas Matelan:
The FLEX/32 Multicomputer.
209-213
- Dick Naedel:
Closely Coupled Asynchronous Hierarchical and Parallel Processing in an Open Architecture.
215-220
- Jim Savage:
Parallel Processing as a Language Design Problem.
221-224
- David P. Rodgers:
Improvements in Multiprocessor System Design.
225-231
- Peter B. Mark:
The Sequoia Computer: A Fault-Tolerant Tightly-Coupled Multiprocessor Architecture.
232
- Elliot Nestle, Armond Inselberg:
The Synapse N+1 System: Architectural Characteristics and Performance Data of a Tightly-Coupled Multiprocessor System.
233-239
- Robert W. Horst, Timothy C. K. Chou:
An Architecture for High Volume Transaction Processing.
240-245
- Shigeo Kamiya, Kazuhide Iwata, Hiroshi Sakai, Susumu Matsuda, Shigeki Shibayama, Kunio Murakami:
A Hardware Pipeline Algorithm for Relational Database Operation and Its Implementation Using Dedicated Hardware.
250-257
- Dik Lun Lee:
A Distributed Multiple-Response Resolver for Value-Ordered Retrieval.
258-265
- John Feo, Roy M. Jenevein, James C. Browne:
Dynamic, Distributed Resource Configuration on SW-Banyans.
268-275
- Randy H. Katz, Susan J. Eggers, David A. Wood, C. L. Perkins, R. G. Sheldon:
Implementing A Cache Consistency Protocol.
276-283
- Zhiyuan Li, Walid A. Abu-Sufah:
A Technique for Reducing Synchronization Overhead in Large Scale Multiprocessors.
284-291
- Colin Whitby-Strevens:
The Transputer.
292-300
- Ali R. Hurson, Behrooz Shirazi:
A Systolic Multiplier Unit and Its VLSI Design.
302-309
- Rami G. Melhem:
A Language for the Simulation of Systolic Architectures.
310-314
- Henry Y. H. Chuang, Guo He:
A Versatile Systolic Array for Matrix Computations.
315-322
- Rex W. Vedder, Dennis Finn:
The Hughes Data Flow Multiprocessor: Architecture for Efficient Signal and Data Processing.
324-332
- Kenneth R. Traub:
An Abstract Parallel Graph Reduction Machine.
333-341
- Bruno R. Preiss, V. Carl Hamacher:
Data Flow on a Queue Machine.
342-351
- Jean-Luc Gaudiot:
Methods for Handling Structures in Data-Flow Systems.
352-358
- Maheswara R. Samatham, Dhiraj K. Pradhan:
The de Bruijn Multiprocessor Network: A Versatile Sorting Network.
360-367
- Nian-Feng Tzeng, Pen-Chung Yew, Chuan-Qi Zhu:
Fault-Tolerant Scheme for Multistage Interconnection Networks.
368-375
- Vijay P. Kumar, Sudhakar M. Reddy:
Design and Analysis of Fault-Tolerant Multistage Interconnection Networks With Low Link Complexity.
376-386
- Nathaniel J. Davis IV, Howard Jay Siegel:
The Performance Analysis of Partitioned Circuit Switched Multistage Interconnection Networks.
387-394
- Dalibor F. Vrsalovic, Edward F. Gehringer, Zary Segall, Daniel P. Siewiorek:
The Influence of Parallel Decomposition Strategies on the Performance of Multiprocessor Systems.
396-405
- Walid A. Abu-Sufah, Alex Y. Kwok:
Performance Prediction Tools for Cedar: A Multiprocessor Supercomputer.
406-413
- José M. Llabería, Mateo Valero, Enrique Herrada Lillo, Jesús Labarta:
Analysis and Simulation of Multiplexed Single-Bus Networks With and Without Buffering.
414-421
- John Sanguinetti, B. Kumar:
Performance of a Message-Based Multiprocessor.
424-425
Copyright © Mon Nov 2 20:52:02 2009
by Michael Ley (ley@uni-trier.de)
