| * | 2009 |
|---|
| 14 | EE | Ki-Sang Jung,
Kang-Jik Kim,
Yong-Eun Kim,
Jin-Gyun Chung,
Ki-Hyun Pyun,
Jong-Yeol Lee,
Hang-Geun Jeong,
Seong Ik Cho:
The ROM Design with Half Grouping Compression Method for Chip Area and Power Consumption Reduction.
IEICE Transactions 92-C(3): 352-355 (2009) |
| 2008 |
|---|
| 13 | EE | Yong-Eun Kim,
Su-Hyun Cho,
Jin-Gyun Chung:
Modified CSD group multiplier design for predetermined coefficient groups.
ISCAS 2008: 3362-3365 |
| 2007 |
|---|
| 12 | EE | Sun-Ah Hong,
Yong-Eun Kim,
Jin-Gyun Chung,
Sung-Chul Lee:
Efficient Squarer Design Using Group Partial Products.
SiPS 2007: 146-150 |
| 11 | EE | Kyung-Ju Cho,
Yi-Nan Xu,
Jin-Gyun Chung:
Hardware Efficient QR Decomposition for GDFE.
SiPS 2007: 412-417 |
| 10 | EE | Yong-Eun Kim,
Kyung-Ju Cho,
Jin-Gyun Chung:
Low Power Small Area Modified Booth Multiplier Design for Predetermined Coefficients.
IEICE Transactions 90-A(3): 694-697 (2007) |
| 9 | EE | Kyung-Ju Cho,
Jin-Gyun Chung:
Adaptive Error Compensation for Low Error Fixed-Width Squarers.
IEICE Transactions 90-D(3): 621-626 (2007) |
| 2004 |
|---|
| 8 | EE | Dae-Ik Kim,
Sung-Hwan Bae,
Mike Myung-Ok Lee,
Jin-Gyun Chung:
Area Efficient and Low Power Pipelined IIR Filter Design for Intelligent Integrated Photonic System.
HSNMC 2004: 842-847 |
| 7 | | Kyung-Ju Cho,
Kwang-Chul Lee,
Jin-Gyun Chung,
Keshab K. Parhi:
Design of low-error fixed-width modified booth multiplier.
IEEE Trans. VLSI Syst. 12(5): 522-531 (2004) |
| 2003 |
|---|
| 6 | EE | Ji-Suk Park,
Byeong-Kuk Kim,
Jin-Gyun Chung,
Keshab K. Parhi:
High-speed tunable fractional-delay allpass filter structure.
ISCAS (4) 2003: 165-168 |
| 5 | EE | Hojun Kim,
Jin-Gyun Chung:
Minimizing switching activity in input word by offset and its low power applications for FIR filters.
ISCAS (5) 2003: 297-300 |
| 2002 |
|---|
| 4 | EE | Sang-Min Kim,
Jin-Gyun Chung,
Keshab K. Parhi:
Design of low error CSD fixed-width multiplier.
ISCAS (1) 2002: 69-72 |
| 2001 |
|---|
| 3 | EE | Ki-Cheol Tae,
Jin-Gyun Chung,
Dae-Ik Kim:
Noise generation system using DCT.
ISCAS (4) 2001: 29-32 |
| 1995 |
|---|
| 2 | | Jin-Gyun Chung,
Keshab K. Parhi:
Synthesis and Pipelining of Ladder Wave Digital Filters in Digital Domain.
ISCAS 1995: 77-80 |
| 1993 |
|---|
| 1 | | Jin-Gyun Chung,
Keshab K. Parhi:
The scaled normalized lattice digital filter.
ISCAS 1993: 483-486 |
