Frank Hannig Vis

*	2009
38	EE	Frank Hannig, Hritam Dutta, Jürgen Teich: Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning. ARCS 2009: 16-27
37	EE	Hritam Dutta, Frank Hannig, Jürgen Teich: Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis. ARCS 2009: 233-245
36	EE	Hritam Dutta, Jiali Zhai, Frank Hannig, Jürgen Teich: Impact of Loop Tiling on the Controller Logic of Acceleration Engines. ASAP 2009: 161-168
35	EE	Richard Membarth, Philipp Kutzer, Hritam Dutta, Frank Hannig, Jürgen Teich: Acceleration of Multiresolution Imaging Algorithms: A Comparative Study. ASAP 2009: 211-214
34	EE	Joachim Keinert, Hritam Dutta, Frank Hannig, Christian Haubelt, Jürgen Teich: Model-based synthesis and optimization of static multi-rate image processing algorithms. DATE 2009: 135-140
33	EE	Richard Membarth, Frank Hannig, Hritam Dutta, Jürgen Teich: Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors. SAMOS 2009: 277-288
32	EE	Hritam Dutta, Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich, Bernard Pottier: A holistic approach for tightly coupled reconfigurable parallel processors. Microprocessors and Microsystems - Embedded Hardware Design 33(1): 53-62 (2009)
	2008
31	EE	Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Jürgen Teich: PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. ARC 2008: 284-289
30	EE	Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig: Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures. DSD 2008: 345-352
29	EE	Rainer Schaffer, Renate Merker, Frank Hannig, Jürgen Teich: Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism. DSD 2008: 391-398
28	EE	Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig: Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures. FCCM 2008: 306-309
27	EE	Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner: Coarse-grained reconfiguration. FPL 2008: 349
26	EE	Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig: Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures. FPL 2008: 391-396
25	EE	Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich: Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. PATMOS 2008: 307-317
	2007
24	EE	Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement: Modeling of Interconnection Networks in Massively Parallel Processor Architectures. ARCS 2007: 268-282
23		Jürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, Andrej Stravet: A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation. ERSA 2007: 14-24
22		Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier: Massively Parallel Processor Architectures: A Co-design Approach. ReCoSoC 2007: 61-68
21	EE	Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jürgen Teich: Efficient event-driven simulation of parallel processor architectures. SCOPES 2007: 71-80
20	EE	Hritam Dutta, Frank Hannig, Holger Ruckdeschel, Jürgen Teich: Efficient control generation for mapping nested loop programs onto processor arrays. Journal of Systems Architecture 53(5-6): 300-309 (2007)
	2006
19	EE	Hritam Dutta, Frank Hannig, Jürgen Teich: Controller Synthesis for Mapping Partitioned Programs on Array Architectures. ARCS 2006: 176-190
18	EE	Hritam Dutta, Frank Hannig, Jürgen Teich, Benno Heigl, Heinz Hornegger: A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. ASAP 2006: 331-340
17		Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich: A Generic Framework for Rapid Prototyping of System-on-Chip Designs. CDES 2006: 189-195
16	EE	Hritam Dutta, Frank Hannig, Jürgen Teich: Hierarchical Partitioning for Piecewise Linear Algorithms. PARELEC 2006: 153-160
15		Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich: A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template. ReCoSoC 2006: 31-37
14	EE	Frank Hannig, Hritam Dutta, Jürgen Teich: Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology. IJES 2(1/2): 114-127 (2006)
	2005
13	EE	Thomas Schlichter, Christian Haubelt, Frank Hannig, Jürgen Teich: Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems. ASAP 2005: 9-14
12		Frank Hannig, Jürgen Teich: Output Serialization for FPGA-based and Coarse-grained Processor Arrays. ERSA 2005: 78-84
11		Jan van der Veen, Sándor P. Fekete, Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich: Defragmenting the Module Layout of a Partially Reconfigurable Device. ERSA 2005: 92-104
10		Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Menard, Olivier Sentieys: Co-Design of Massively Parallel Embedded Processor Architectures. ReCoSoC 2005: 27-34
9	EE	Holger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich: Automatic FIR Filter Generation for FPGAs. SAMOS 2005: 51-61
8	EE	Jan van der Veen, Sándor P. Fekete, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich: Defragmenting the Module Layout of a Partially Reconfigurable Device CoRR abs/cs/0505005: (2005)
	2004
7	EE	Frank Hannig, Jürgen Teich: Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals. ASAP 2004: 17-27
6	EE	Frank Hannig, Hritam Dutta, Jürgen Teich: Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology. IPDPS 2004
5	EE	Frank Hannig, Jürgen Teich: Dynamic Piecewise Linear/Regular Algorithms. PARELEC 2004: 79-84
4	EE	Alexey Kupriyanov, Frank Hannig, Jürgen Teich: High-Speed Event-Driven RTL Compiled Simulation. SAMOS 2004: 519-529
	2002
3	EE	Marcus Bednara, Frank Hannig, Jürgen Teich: Generation of Distributed Loop Control. Embedded Processor Design Challenges 2002: 154-170
2	EE	Frank Hannig, Jürgen Teich: Energy estimation of nested loop programs. SPAA 2002: 149-150
	2001
1	EE	Frank Hannig, Jürgen Teich: Design Space Exploration for Massively Parallel Processor Arrays. PaCT 2001: 51-65

Coauthor Index

1	Ali Ahmadinia	[8] [11]
2	Jürgen Becker	[27]
3	Marcus Bednara	[3]
4	Christophe Bobda	[8] [11]
5	Daniel Chillet	[10]
6	Hritam Dutta	[6] [9] [10] [14] [16] [18] [19] [20] [22] [23] [27] [31] [32] [33] [34] [35] [36] [37] [38]
7	Sven Eisenhardt	[27]
8	Sándor P. Fekete	[8] [11]
9	Julio A. de Oliveira Filho	[27]
10	Manfred Glesner	[27]
11	Christian Haubelt	[13] [34]
12	Benno Heigl	[18]
13	Heiko Hinkelmann	[27]
14	Heinz Hornegger	[18]
15	Joachim Keinert	[34]
16	Ronan Keryell	[10]
17	Dmitrij Kissler	[15] [17] [21] [22] [23] [24] [25] [27] [32]
18	Dirk Koch	[17]
19	Krzysztof Kuchcinski	[26] [28] [30]
20	Alexey Kupriyanov	[4] [10] [15] [17] [21] [22] [24] [32]
21	Philipp Kutzer	[35]
22	Julien Lallet	[24]
23	Mateusz Majer	[11]
24	Richard Membarth	[33] [35]
25	Daniel Menard	[10]
26	Renate Merker	[10] [22] [29]
27	Tobias Oppold	[27]
28	Sébastien Pillement	[24]
29	Bernard Pottier	[10] [22] [32]
30	Wolfgang Rosenstiel	[27]
31	Holger Ruckdeschel	[9] [20] [23] [31]
32	Rainer Schaffer	[10] [22] [29]
33	Thomas Schlichter	[13]
34	Thomas Schweizer	[27]
35	Olivier Sentieys	[10] [24]
36	Sebastian Siegel	[10] [22]
37	Andrej Stravet	[23]
38	Andreas Strawetz	[25]
39	Jürgen Teich	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38]
40	Alexander Thomas	[27]
41	Jan van der Veen	[8] [11]
42	Christophe Wolinski	[26] [28] [30]
43	Jiali Zhai	[36]
44	Peter Zipf	[27]