| 2008 |
|---|
| 70 | EE | Iyad Al Khatib,
Francesco Poletti,
Davide Bertozzi,
Luca Benini,
Mohamed Bechara,
Hasan Khalifeh,
Axel Jantsch,
Rustam Nabiev:
A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration.
ACM Trans. Design Autom. Electr. Syst. 13(2): (2008) |
| 2007 |
|---|
| 69 | EE | Tarvo Raudvere,
Ingo Sander,
Axel Jantsch:
A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loops.
ACM Great Lakes Symposium on VLSI 2007: 353-358 |
| 68 | EE | Tarvo Raudvere,
Ingo Sander,
Axel Jantsch:
Synchronization after design refinements with sensitive delay elements.
CODES+ISSS 2007: 21-26 |
| 67 | EE | Iyad Al Khatib,
Davide Bertozzi,
Axel Jantsch,
Luca Benini:
Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions.
CODES+ISSS 2007: 217-226 |
| 66 | EE | Zhonghai Lu,
Ming Liu,
Axel Jantsch:
Layered Switching for Networks on Chip.
DAC 2007: 122-127 |
| 65 | EE | Zhonghai Lu,
Axel Jantsch:
Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip.
ICCAD 2007: 18-25 |
| 64 | EE | Zhonghai Lu,
Jonas Sicking,
Ingo Sander,
Axel Jantsch:
Using Synchronizers for Refining Synchronous Communication onto Hardware/Software Architectures.
IEEE International Workshop on Rapid System Prototyping 2007: 143-149 |
| 63 | EE | Cristian Grecu,
André Ivanov,
Partha Pratim Pande,
Axel Jantsch,
Erno Salminen,
Ümit Y. Ogras,
Radu Marculescu:
Towards Open Network-on-Chip Benchmarks.
NOCS 2007: 205 |
| 62 | EE | Per Badlund,
Axel Jantsch:
An Analytical Approach for Dimensioning Mixed Traffic Networks.
NOCS 2007: 215 |
| 61 | EE | Mikael Millberg,
Axel Jantsch:
A Study of NoC Exit Strategies.
NOCS 2007: 217 |
| 60 | EE | Deepak Mathaikutty,
Hiren D. Patel,
Sandeep K. Shukla,
Axel Jantsch:
EWD: A metamodeling driven customizable multi-MoC system modeling framework.
ACM Trans. Design Autom. Electr. Syst. 12(3): (2007) |
| 59 | EE | Erik Jan Marinissen,
Axel Jantsch,
Nicola Nicolici:
DATE 07 workshop on diagnostic services in NoCs.
IEEE Design & Test of Computers 24(5): 510 (2007) |
| 2006 |
|---|
| 58 | EE | Zhonghai Lu,
Mingchen Zhong,
Axel Jantsch:
Evaluation of on-chip networks using deflection routing.
ACM Great Lakes Symposium on VLSI 2006: 296-301 |
| 57 | EE | Tiberiu Seceleanu,
Axel Jantsch:
Communicating with Synchronized Environments.
ACSD 2006: 15-24 |
| 56 | EE | Axel Jantsch:
Models of Computation for Networks on Chip.
ACSD 2006: 165-178 |
| 55 | EE | Iyad Al Khatib,
Davide Bertozzi,
Francesco Poletti,
Luca Benini,
Axel Jantsch,
Mohamed Bechara,
Hasan Khalifeh,
Mazen Hajjar,
Rustam Nabiev,
Sven Jonsson:
MPSoC ECG biochip: a multiprocessor system-on-chip for real-time human heart monitoring and analysis.
Conf. Computing Frontiers 2006: 21-28 |
| 54 | EE | Iyad Al Khatib,
Francesco Poletti,
Davide Bertozzi,
Luca Benini,
Mohamed Bechara,
Hasan Khalifeh,
Axel Jantsch,
Rustam Nabiev:
A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration.
DAC 2006: 125-130 |
| 53 | EE | Zhonghai Lu,
Ingo Sander,
Axel Jantsch:
Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication.
DSD 2006: 37-44 |
| 52 | EE | Guang Liang,
Axel Jantsch:
Adaptive Power Management for the On-Chip Communication Network.
DSD 2006: 649-656 |
| 51 | EE | Sandro Penolazzi,
Axel Jantsch:
A High Level Power Model for the Nostrum NoC.
DSD 2006: 673-676 |
| 50 | EE | Rikard Thid,
Ingo Sander,
Axel Jantsch:
Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads.
DSD 2006: 681-688 |
| 49 | EE | Zhonghai Lu,
Bei Yin,
Axel Jantsch:
Connection-oriented Multicasting in Wormhole-switched Networks on Chip.
ISVLSI 2006: 205-2110 |
| 48 | EE | Weixing Wang,
Axel Jantsch:
An algorithm for electing cluster heads based on maximum residual energy.
IWCMC 2006: 1465-1470 |
| 2005 |
|---|
| 47 | | Petru Eles,
Axel Jantsch,
Reinaldo A. Bergamaschi:
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005
ACM 2005 |
| 46 | EE | Zhonghai Lu,
Axel Jantsch,
Ingo Sander:
Feasibility analysis of messages for on-chip networks using wormhole routing.
ASP-DAC 2005: 960-964 |
| 45 | | Tarvo Raudvere,
Ashish Kumar Singh,
Ingo Sander,
Axel Jantsch:
System level verification of digital signal processing applications based on the polynomial abstraction technique.
ICCAD 2005: 285-290 |
| 44 | EE | Axel Jantsch,
Robert Lauter,
Arseni Vitkovski:
Power analysis of link level and end-to-end data protection in networks on chip.
ISCAS (2) 2005: 1770-1773 |
| 43 | EE | Zhonghai Lu,
Axel Jantsch:
Traffic Configuration for Evaluating Networks on Chips.
IWSOC 2005: 535-540 |
| 2004 |
|---|
| 42 | | Alex Orailoglu,
Pai H. Chou,
Petru Eles,
Axel Jantsch:
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004
ACM 2004 |
| 41 | EE | Abhijit K. Deb,
Axel Jantsch,
Johnny Öberg:
System design for DSP applications in transaction level modeling paradigm.
DAC 2004: 466-471 |
| 40 | EE | Abhijit K. Deb,
Axel Jantsch,
Johnny Öberg:
System Design for DSP Applications Using the MASIC Methodology.
DATE 2004: 630-635 |
| 39 | EE | Tarvo Raudvere,
Ashish Kumar Singh,
Ingo Sander,
Axel Jantsch:
Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits.
DATE 2004: 690-691 |
| 38 | EE | Mikael Millberg,
Erland Nilsson,
Rikard Thid,
Axel Jantsch:
Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip.
DATE 2004: 890-895 |
| 37 | EE | Mikael Millberg,
Erland Nilsson,
Rikard Thid,
Shashi Kumar,
Axel Jantsch:
The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip.
VLSI Design 2004: 693-696 |
| 36 | EE | Ingo Sander,
Axel Jantsch:
System modeling and transformational design refinement in ForSyDe [formal system design].
IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 17-32 (2004) |
| 35 | EE | Dinesh Pamunuwa,
Johnny Öberg,
Li-Rong Zheng,
Mikael Millberg,
Axel Jantsch,
Hannu Tenhunen:
A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime.
Integration 38(1): 3-17 (2004) |
| 34 | EE | Axel Jantsch,
Johnny Öberg,
Hannu Tenhunen:
Special issue on networks on chip.
Journal of Systems Architecture 50(2-3): 61-63 (2004) |
| 2003 |
|---|
| 33 | EE | Tarvo Raudvere,
Ingo Sander,
Ashish Kumar Singh,
Axel Jantsch:
Verification of design decisions in ForSyDe.
CODES+ISSS 2003: 176-181 |
| 32 | EE | Heiko Zimmer,
Axel Jantsch:
A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip.
CODES+ISSS 2003: 188-193 |
| 31 | EE | Ingo Sander,
Axel Jantsch,
Zhonghai Lu:
Development and Application of Design Transformations in ForSyDe.
DATE 2003: 10364-10369 |
| 30 | EE | Abhijit K. Deb,
Johnny Öberg,
Axel Jantsch:
Simulation and Analysis of Embedded DSP Systems Using MASIC Methodology.
DATE 2003: 11100-11101 |
| 29 | EE | Erland Nilsson,
Mikael Millberg,
Johnny Öberg,
Axel Jantsch:
Load Distribution with the Proximity Congestion Awareness in a Network on Chip.
DATE 2003: 11126-11127 |
| 28 | EE | Axel Jantsch:
NoCs: A new Contract between Hardware and Software.
DSD 2003: 10-16 |
| 27 | EE | Abhijit K. Deb,
Johnny Öberg,
Axel Jantsch:
Simulation and Analysis of Embedded DSP Systems Using Petri Nets.
IEEE International Workshop on Rapid System Prototyping 2003: 64-70 |
| 26 | EE | Juha-Pekka Soininen,
Axel Jantsch,
Martti Forsell,
Antti Pelkonen,
Jari Kreku,
Shashi Kumar:
Extending Platform-Based Design to Network on Chip Systems.
VLSI Design 2003: 401- |
| 25 | | Dinesh Pamunuwa,
Johnny Öberg,
Li-Rong Zheng,
Mikael Millberg,
Axel Jantsch:
Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures.
VLSI-SOC 2003: 362- |
| 2002 |
|---|
| 24 | EE | Per Bjuréus,
Mikael Millberg,
Axel Jantsch:
FPGA resource and timing estimation from Matlab execution traces.
CODES 2002: 31-36 |
| 23 | EE | Ingo Sander,
Axel Jantsch:
Transformation based communication and clock domain refinement for system design.
DAC 2002: 281-286 |
| 22 | EE | Ingo Sander,
Axel Jantsch,
Zhonghai Lu:
A Case Study of Hardware and Software Synthesis in ForSyDe.
ISSS 2002: 86-91 |
| 21 | EE | Shashi Kumar,
Axel Jantsch,
Mikael Millberg,
Johnny Öberg,
Juha-Pekka Soininen,
Martti Forsell,
Kari Tiensyrjä,
Ahmed Hemani:
A Network on Chip Architecture and Design Methodology.
ISVLSI 2002: 117-124 |
| 2001 |
|---|
| 20 | EE | Axel Jantsch,
Ingo Sander,
Wenbiao Wu:
The usage of stochastic processes in embedded system specifications.
CODES 2001: 5-10 |
| 19 | | Abhijit K. Deb,
Johnny Öberg,
Axel Jantsch:
Control and communication performance analysis of embedded DSP systems in the MASIC methodology.
ISSS 2001: 274-273 |
| 18 | | Per Bjuréus,
Axel Jantsch:
Performance analysis with confidence intervals for embedded software processes.
ISSS 2001: 45-50 |
| 17 | EE | Per Bjuréus,
Axel Jantsch:
Modeling of mixed control and dataflow systems in MASCOT.
IEEE Trans. VLSI Syst. 9(5): 690-703 (2001) |
| 2000 |
|---|
| 16 | EE | Axel Jantsch,
Ingo Sander:
On the roles of functions and objects in system specification.
CODES 2000: 8-12 |
| 15 | EE | Axel Jantsch,
Per Bjuréus:
Composite Signal Flow: A Computational Model Combining Events, Sampled Streams, and Vectors.
DATE 2000: 154-160 |
| 14 | EE | Per Bjuréus,
Axel Jantsch:
MASCOT: A Specification and Cosimulation Method Integrating Data and Control Flow.
DATE 2000: 161-168 |
| 13 | EE | Johan Ditmar,
Kjell Torkelsson,
Axel Jantsch:
A Dynamically Reconfigurable FPGA-Based Content Addressable Memory for Internet Protocol Characterization.
FPL 2000: 19-28 |
| 12 | EE | Axel Jantsch,
Shashi Kumar,
Ahmed Hemani:
A Metamodel for Studying Concepts in Electronic System Design.
IEEE Design & Test of Computers 17(3): 78-85 (2000) |
| 1999 |
|---|
| 11 | EE | Ingo Sander,
Axel Jantsch:
System synthesis utilizing a layered functional model.
CODES 1999: 136-140 |
| 10 | EE | Axel Jantsch,
Shashi Kumar,
Ahmed Hemani:
The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems.
DATE 1999: 256-262 |
| 9 | EE | Mattias O'Nils,
Axel Jantsch:
Operating System Sensitive Device Driver Synthesis from Implementation Independent Protocol Specification.
DATE 1999: 562-567 |
| 8 | EE | Mattias O'Nils,
Axel Jantsch:
Synthesis of DMA Controllers from Architecture Independent Descriptions of HW/SW Communication Protocols.
VLSI Design 1999: 138-145 |
| 7 | | Ingo Sander,
Axel Jantsch:
Formal System Design Based on the Synchrony Hypothesis, Functional Models and Skeletons.
VLSI Design 1999: 318-323 |
| 1998 |
|---|
| 6 | EE | Mattias O'Nils,
Johnny Öberg,
Axel Jantsch:
Grammar Based Modelling and Synthesis of Device Drivers and Bus Interfaces.
EUROMICRO 1998: 10055-10058 |
| 5 | EE | Johnny Öberg,
Axel Jantsch,
Anshul Kumar:
An Object-Oriented Concept for Intelligent Library Functions.
VLSI Design 1998: 355-358 |
| 1996 |
|---|
| 4 | EE | Johnny Öberg,
Jouni Isoaho,
Peeter Ellervee,
Axel Jantsch,
Ahmed Hemani:
A Rule-Based Approach for Improving Allocation of Filter Structures in HLS.
VLSI Design 1996: 133-139 |
| 3 | EE | Bengt Svantesson,
Ahmed Hemani,
Peeter Ellervee,
Adam Postula,
Johnny Öberg,
Axel Jantsch,
Hannu Tenhunen:
A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts.
VLSI Design 1996: 23-28 |
| 1994 |
|---|
| 2 | EE | Axel Jantsch,
Peeter Ellervee,
Ahmed Hemani,
Johnny Öberg,
Hannu Tenhunen:
Hardware/software partitioning and minimizing memory interface traffic.
EURO-DAC 1994: 226-231 |
| 1 | | Jouni Isoaho,
Axel Jantsch,
Hannu Tenhunen:
DSP Development with Full-Speed Prototyping Based on HW/SW Codesign Techniques.
FPL 1994: 318-320 |
