| * | 2009 |
|---|
| 8 | EE | Gang Zhou,
Harald Michalik,
László Hinsenkamp:
Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs.
ARC 2009: 193-203 |
| 7 | EE | Björn Osterloh,
Harald Michalik,
Björn Fiethe:
SoCWire: A Robust and Fault Tolerant Network-on-Chip Approach for a Dynamic Reconfigurable System-on-Chip in FPGAs.
ARCS 2009: 50-59 |
| 6 | | Yannick Dadji Foyet,
Harald Michalik,
Tobias Möglich:
Parallel Architecture For Real Time Control System Based On The IEEE1394 Standard.
PDPTA 2009: 24-29 |
| 2008 |
|---|
| 5 | | Yannick Dadji,
Jochen Maass,
Harald Michalik,
Tobias Möglich,
N. Kohn,
J. Uwe Varchmin:
Networked Architecture for Distributed PC-based Robot Control Systems.
ARCS 2008: 204-211 |
| 4 | EE | Gang Zhou,
Li Li,
Harald Michalik:
Area optimization of bit parallel finite field multipliers with fast carry logic on FPGAS.
FPL 2008: 671-674 |
| 2007 |
|---|
| 3 | EE | Björn Osterloh,
Harald Michalik,
Björn Fiethe,
F. Bubenhagen:
Enhancements of reconfigurable System-on-Chip Data Processing Units for Space Application.
AHS 2007: 258-262 |
| 2 | EE | Björn Fiethe,
Harald Michalik,
C. Dierker,
Björn Osterloh,
Gang Zhou:
Reconfigurable system-on-chip data processing units for space imaging instruments.
DATE 2007: 977-982 |
| 1986 |
|---|
| 1 | | E. Krahn,
Fritz Gliem,
Harald Michalik,
Peter Rüffer:
Der Instrumentenrechner der Halley Multicolour Camera.
ARCS 1986: 72-83 |
