Michael Orshansky

2007
30	EE	Rajeshwary Tayade, Vijay Kiran Kalyanam, Sani R. Nassif, Michael Orshansky, Jacob Abraham: Estimating path delay distribution considering coupling noise. ACM Great Lakes Symposium on VLSI 2007: 61-66
29	EE	Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan: Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis. DAC 2007: 148-153
28	EE	Ashish Kumar Singh, Adnan Aziz, Sriram Vishwanath, Michael Orshansky: Generation of Efficient Codes for Realizing Boolean Functions in Nanotechnologies CoRR abs/cs/0703102: (2007)
27	EE	Murari Mani, Anirudh Devgan, Michael Orshansky, Yaping Zhan: A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1790-1802 (2007)
26	EE	Wei-Shen Wang, Michael Orshansky: Estimation of Leakage Power Consumption and Parametric Yield Based on Realistic Probabilistic Descriptions of Parameters. J. Low Power Electronics 3(1): 1-12 (2007)
25	EE	Kypros Constantinides, Stephen Plaza, Jason A. Blome, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Bin Zhang, Michael Orshansky: Architecting a reliable CMP switch architecture. TACO 4(1): (2007)
2006
24	EE	Joonsoo Kim, Michael Orshansky: Towards formal probabilistic power-performance design space exploration. ACM Great Lakes Symposium on VLSI 2006: 229-234
23	EE	Murari Mani, Mahesh Sharma, Michael Orshansky: Application of fast SOCP based statistical sizing in the microprocessor design flow. ACM Great Lakes Symposium on VLSI 2006: 372-375
22	EE	Wei-Shen Wang, Vladik Kreinovich, Michael Orshansky: Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty. DAC 2006: 161-166
21	EE	Ashish Kumar Singh, Murari Mani, Ruchir Puri, Michael Orshansky: Gain-based technology mapping for minimum runtime leakage under input vector uncertainty. DAC 2006: 522-527
20	EE	Murari Mani, Ashish Kumar Singh, Michael Orshansky: Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization. ICCAD 2006: 19-26
19	EE	Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan: An accurate sparse matrix based framework for statistical static timing analysis. ICCAD 2006: 231-236
18	EE	Bin Zhang, Ari Arapostathis, Sani R. Nassif, Michael Orshansky: Analytical modeling of SRAM dynamic stability. ICCAD 2006: 315-322
17	EE	Wei-Shen Wang, Michael Orshansky: Robust estimation of parametric yield under limited descriptions of uncertainty. ICCAD 2006: 884-890
16	EE	Keith A. Bowman, Michael Orshansky, Sachin S. Sapatnekar: Tutorial II: Variability and Its Impact on Design. ISQED 2006: 5
15	EE	Bin Zhang, Wei-Shen Wang, Michael Orshansky: FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs. ISQED 2006: 755-760
14	EE	Michael Orshansky, Wei-Shen Wang, Martine Ceberio, Gang Xiang: Interval-based robust statistical techniques for non-negative convex functions, with application to timing analysis of computer chips. SAC 2006: 1645-1649
13	EE	Wei-Shen Wang, Michael Orshansky: Path-Based Statistical Timing Analysis Handling Arbitrary Delay Correlations: Theory and Implementation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2976-2988 (2006)
12	EE	Wei-Shen Wang, Michael Liu, Michael Orshansky: Analysis of Leakage Power Reduction in Dual-Vth Technologies in the Presence of Large Threshold Voltage Variation. J. Low Power Electronics 2(1): 1-7 (2006)
2005
11	EE	Murari Mani, Anirudh Devgan, Michael Orshansky: An efficient algorithm for statistical minimization of total power under timing yield constraints. DAC 2005: 309-314
10		Ashish Kumar Singh, Murari Mani, Michael Orshansky: Statistical technology mapping for parametric yield. ICCAD 2005: 511-518
2004
9	EE	Michael Orshansky, Arnab Bandyopadhyay: Fast statistical timing analysis handling arbitrary delay correlations. DAC 2004: 337-342
8	EE	Murari Mani, Michael Orshansky: A New Statistical Optimization Algorithm for Gate Sizing. ICCD 2004: 272-277
7	EE	Michael Liu, Wei-Shen Wang, Michael Orshansky: Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation. ISLPED 2004: 2-7
2003
6	EE	David Nguyen, Abhijit Davare, Michael Orshansky, David G. Chinnery, Brandon Thompson, Kurt Keutzer: Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization. ISLPED 2003: 158-163
2002
5	EE	Michael Orshansky, Kurt Keutzer: A general probabilistic framework for worst case timing analysis. DAC 2002: 556-561
4	EE	Kurt Keutzer, Michael Orshansky: From blind certainty to informed uncertainty. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 37-41
3	EE	Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu: Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 21(5): 544-553 (2002)
2000
2		Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu: Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits. ICCAD 2000: 62-67
1998
1	EE	Michael Orshansky, James C. Chen, Chenming Hu: A Statistical Performance Simulation Methodology for VLSI Circuits. DAC 1998: 402-407

Coauthor Index

1	Jacob Abraham	[30]
2	Ari Arapostathis	[18]
3	Todd M. Austin	[25]
4	Adnan Aziz	[28]
5	Arnab Bandyopadhyay	[9]
6	Valeria Bertacco	[25]
7	Jason A. Blome	[25]
8	Keith A. Bowman	[16]
9	Martine Ceberio	[14]
10	James C. Chen	[1]
11	Pinhong Chen	[2] [3]
12	David G. Chinnery	[6]
13	Kypros Constantinides	[25]
14	Abhijit Davare	[6]
15	Anirudh Devgan	[11] [27]
16	Chenming Hu	[1] [2] [3]
17	Vijay Kiran Kalyanam	[30]
18	Kurt Keutzer	[2] [3] [4] [5] [6]
19	Joonsoo Kim	[24]
20	Vladik Kreinovich	[22]
21	Michael Liu	[7] [12]
22	Scott A. Mahlke	[25]
23	Murari Mani	[8] [10] [11] [20] [21] [23] [27]
24	Linda S. Milor (Linda Milor)	[2] [3]
25	Gi-Joon Nam	[19]
26	Sani R. Nassif	[18] [19] [29] [30]
27	David Nguyen	[6]
28	David Z. Pan (David Zhigang Pan)	[19] [29]
29	Stephen Plaza	[25]
30	Ruchir Puri	[21]
31	Anand Ramalingam	[19] [29]
32	Sachin S. Sapatnekar	[16]
33	Mahesh Sharma	[23]
34	Ashish Kumar Singh	[10] [19] [20] [21] [28] [29]
35	Rajeshwary Tayade	[30]
36	Brandon Thompson	[6]
37	Sriram Vishwanath	[28]
38	Wei-Shen Wang	[7] [12] [13] [14] [15] [17] [22] [26]
39	Gang Xiang	[14]
40	Yaping Zhan	[27]
41	Bin Zhang	[15] [18] [25]

Colors in the list of coauthors