| 2007 |
| 23 | EE | Christopher Claus,
Johannes Zeppenfeld,
Florian Helmut Müller,
Walter Stechele:
Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system.
DATE 2007: 498-503 |
| 22 | EE | Christopher Claus,
Florian Helmut Müller,
Johannes Zeppenfeld,
Walter Stechele:
A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration.
IPDPS 2007: 1-7 |
| 21 | EE | Michael Hübner,
Lars Braun,
Jürgen Becker,
Christopher Claus,
Walter Stechele:
Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs.
ISVLSI 2007: 41-46 |
| 20 | EE | Walter Stechele,
L. Alvado Cárcel,
Stephan Herrmann,
J. Lidón Simón:
A Coprocessor for Accelerating Visual Information Processing
CoRR abs/0710.4823: (2007) |
| 19 | EE | Christopher Claus,
Walter Stechele,
Andreas Herkersdorf:
Autovision - A Run-time Reconfigurable MPSoC Architecture for Future Driver Assistance Systems (Autovision - Eine zur Laufzeit rekonfigurierbare MPSoC Architektur für zukünftige Fahrerassistenzsysteme).
it - Information Technology 49(3): 181- (2007) |
| 2006 |
| 18 | | Christopher Claus,
Florian Helmut Müller,
Walter Stechele:
Combitgen: A new approach for creating partial bitstreams in Virtex-II Pro.
ARCS Workshops 2006: 122-131 |
| 17 | EE | Andreas Herkersdorf,
Walter Stechele:
AutoVision: flexible processor architecture for video-assisted driving.
DATE 2006: 556 |
| 16 | EE | Walter Stechele:
Dynamically Reconfigurable Systems-on-Chip.
Dynamically Reconfigurable Architectures 2006 |
| 15 | | Andreas Bernauer,
Oliver Bringmann,
Wolfgang Rosenstiel,
Abdelmajid Bouajila,
Walter Stechele,
Andreas Herkersdorf:
An Architecture for Runtime Evaluation of SoC Reliability.
GI Jahrestagung (1) 2006: 177- |
| 14 | EE | Abdelmajid Bouajila,
Johannes Zeppenfeld,
Walter Stechele,
Andreas Herkersdorf,
Andreas Bernauer,
Oliver Bringmann,
Wolfgang Rosenstiel:
Organic Computing at the System on Chip Level.
VLSI-SoC 2006: 338-341 |
| 2005 |
| 13 | | Gabriel Lipsa,
Andreas Herkersdorf,
Wolfgang Rosenstiel,
Oliver Bringmann,
Walter Stechele:
Towards a Framework and a Design Methodology for Autonomous SoC.
ARCS Workshops 2005: 101-108 |
| 12 | EE | Walter Stechele,
L. Alvado Cárcel,
Stephan Herrmann,
J. Lidón Simón:
A Coprocessor for Accelerating Visual Information Processing.
DATE 2005: 26-31 |
| 11 | EE | Paul Zuber,
Armin Windschiegl,
Raúl Medina Beltán de Otálora,
Walter Stechele,
Andreas Herkersdorf:
Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization.
DATE 2005: 986-987 |
| 10 | | Paul Zuber,
Florian Helmut Müller,
Walter Stechele:
Optimization Potential of CMOS Power by Wire Spacing.
GI Jahrestagung (1) 2005: 344-348 |
| 9 | EE | Gabriel Lipsa,
Andreas Herkersdorf,
Wolfgang Rosenstiel,
Oliver Bringmann,
Walter Stechele:
Towards a Framework and a Design Methodology for Autonomic SoC.
ICAC 2005: 391-392 |
| 8 | EE | Paul Zuber,
Peter Gritzmann,
Michael Ritter,
Walter Stechele:
The Optimal Wire Order for Low Power CMOS.
PATMOS 2005: 674-683 |
| 2004 |
| 7 | | Walter Stechele,
Stephan Herrmann,
Andreas Herkersdorf:
Towards a Dynamically Reconfigurable System-on-Chip Platform for Video Signal Processing.
ARCS Workshops 2004: 225-234 |
| 2003 |
| 6 | EE | Walter Stechele:
Performance Optimization of Color Segmentation Algorithms.
SIP 2003: 292-297 |
| 2002 |
| 5 | EE | Ulrich Niedermeier,
Jörg Heuer,
Andreas Hutter,
Walter Stechele:
MPEG-7 Binary Format for XML Dat.
DCC 2002: 467 |
| 4 | EE | Michael Eiermann,
Walter Stechele:
Novel modeling techniques for RTL power estimation.
ISLPED 2002: 323-328 |
| 3 | EE | Torsten Mahnke,
Walter Stechele,
Wolfgang Hoeld:
Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment.
PATMOS 2002: 146-155 |
| 2 | EE | Armin Windschiegl,
Paul Zuber,
Walter Stechele:
Exploiting Metal Layer Characteristics for Low-Power Routing.
PATMOS 2002: 55-64 |
| 1997 |
| 1 | EE | Peter M. Kuhn,
Andreas Weisgerber,
Robert Poppenwimmer,
Walter Stechele:
A flexible VLSI architecture for variable block size segment matching with luminance correction.
ASAP 1997: 479-488 |